An Adaptive and High Coding Rate Soft Error Correction Method in Network-on-Chips

Abstract

The soft error rates per single-bit due to alpha particles in sub-micron technology is expectedly reduced
as the feature size is shrinking. On the other hand, the complexity and density of integrated systems are accelerating which demand ecient soft error protection mechanisms, especially for on-chip communication. Using soft error protection method has to satisfy tight requirements for the area and energy consumption, therefore a low complexity and low redundancy coding method is necessary. In this work, we propose a method to enhance Parity Product Code (PPC) and provide adaptation methods for this code. First, PPC is improved as forward error correcting using transposable retransmissions. Then, to adapt with dierent error rates, an augmented algorithm for configuring PPC is introduced. The evaluation results show that the proposed mechanism has coding rates similar to Parity check’s and outperforms the original PPC.
Keywords

Error Correction Code, Fault-Tolerance, Network-on-Chip.

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